发明名称 Method and system for partitioning a verification testbench
摘要 A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.
申请公布号 US9529963(B1) 申请公布日期 2016.12.27
申请号 US201514859158 申请日期 2015.09.18
申请人 Microsemi Storage Solutions (U.S.), Inc. 发明人 Wilson Theodore Andrew
分类号 G06F17/50;G01R31/28 主分类号 G06F17/50
代理机构 代理人 Haszko Dennis R.
主权项 1. A method of testing a design under test (DUT) using a verification test bench, the method comprising: obtaining a computer-readable source code of the DUT and a computer-readable source code of the verification test bench; separating the computer-readable source code of the verification test bench into reactive components and analytic components, the reactive components for sending test traffic to the DUT and for receiving test traffic from the DUT, the analytic components for verifying the test traffic between the reactive components and the DUT; compiling, at a computer processor, the reactive components and the computer-readable source code of the DUT into a first computer-executable test bench; compiling, at the computer processor, the analytic components into a second computer-executable test bench; running the first computer-executable test bench on a simulator program of the computer processor to generate test traffic between the reactive components and the DUT; separately running the second computer-executable test bench on the simulator program of the computer processor to verify the test traffic; and outputting an indication of whether the second computer-executable test bench verified the test traffic as a successful simulation of the DUT or as a failed simulation of the DUT.
地址 Aliso Viejo CA US