| 摘要 |
A parallel bus architecture is disclosed. The parallel bus architecture includes: a first sub-system comprising at least a first master device and at least a first slave device, wherein the first master device can access the first slave directly; a second sub-system comprising at least a second master device and at least a second slave device, wherein the second master device can access the second slave directly; and an interconnect matrix, coupled to the first sub-system and the second sub-system, for transmitting a command from the first sub-system to the second sub-system and transmitting a command from the second sub-system to the first sub-system.
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