Integrated circuits with hold time avoidance circuitry

摘要

Integrated circuits with logic circuitry are provided. The logic circuitry may be organized into logic regions. Each logic region may include a multiplexer, a flip-flop, a logic circuit, etc. The flip-flop may have an input that is connected to an output of the multiplexer. The multiplexer may have a first input connected to an output of the flip-flop in an adjacent logic region. The multiplexer may have a second input connected to the logic circuit. The logic regions may be connected in a chain. The flip-flops may be controlled by first and second control signals. The second control signal may be a delayed version of the first control signal. The multiplexer may be controlled by the second control signal. The flip-flops may include master and slave latches. The master latch is controlled by the first control signal while the slave latch is controlled by the first and second control signals.

主权项

1. Circuitry, comprising:
first and second flip-flops operable as part of a scan chain in a scan mode and operable in a normal operational mode, wherein each of the first and second flip-flops comprises:
a master level-sensitive latch having a master input that serves as an input for the first and second flip-flops and having a master output; anda slave level-sensitive latch having a slave input coupled to the master output and having a slave output that serves as an output for the first and second flip-flops; and control circuitry operable to generate first control signals for the master level-sensitive latch and the slave level-sensitive latch of the first and second flip-flops during the scan mode and operable to generate second control signals for the master level-sensitive latch and the slave level-sensitive latch of the first and second flip-flops during the normal operational mode, wherein the second control signals are different than the first control signals, wherein the first controls signals comprise a first clock signal and a second clock signal that is delayed version of the first clock signal, wherein the master level-sensitive latch of the first flip-flop is operable to receive the first clock signal at a first point in time, wherein the master level-sensitive latch of the second flip-flop is operable to receive the first clock signal at a second point in time that occurs a clock skew delay following the first point in time, wherein the slave level-sensitive latch of the first flip-flop is operable to receive the second clock signal that is delayed with respect to the first clock signal by a delay period that is greater than the clock skew delay.