| 摘要 |
In a step 8 , storage elements contained in sequential circuits are discriminated from each other with respect to circuit design data which contains the sequential circuit which is reset by an asynchronous reset signal and the sequential circuit which is not reset by the asynchronous reset signal. In a step 11 and a step 12 , a flag circuit for indicating as to whether or not the storage element holds valid data is added to each of the storage elements. The flag circuit which is applied to the storage element of the sequential circuit which is not reset by the asynchronous reset signal is brought into an invalid display status which indicates that when the asynchronous reset signal is inputted, the storage element does not hold valid data.
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