| 摘要 |
A processor array including area-saving microprogram memories is provided. In the processor array, microprogram memories of a plurality of adjacent processor arrays are shared. Effective data and position information 13 on the effective data are stored in the shared microprogram memory 3, and effective data parts 11.1 to 11.3 including effective data are accommodated with each other in logic blocks 2a and 2b of a plurality of processor elements. The number of necessary microprogram memories is thereby reduced, thus realizing area saving.
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