发明名称 SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RAIL CIRCUIT
摘要 When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.
申请公布号 US2016275999(A1) 申请公布日期 2016.09.22
申请号 US201615167101 申请日期 2016.05.27
申请人 STMicroelectronics International N.V. 发明人 Chhabra Amit
分类号 G11C5/14;H03K5/08;H03K17/22;H03K3/037 主分类号 G11C5/14
代理机构 代理人
主权项 1. A memory, comprising: a first voltage node configured to ramp up to a first voltage magnitude; a second voltage node having a second voltage magnitude that is greater than the first voltage magnitude; and a sleep mode generation circuit configured to hold a sleep signal at a first logic value until a ramping voltage at the first voltage node exceeds a threshold voltage and the change the sleep signal to a second logic value.
地址 Amsterdam NL