| 摘要 |
A digital multiplier for multiplying together first and second numbers when the first number is a quotient of an integer divided by an integer power of two and the second number has n bits. The multiplier comprises a first register having n-bits, a second register having n+1 bits and a third register having n+2 bits. The first register receives the n-bit second number. The n least significant stages of the second and third registers receive the n-bits of the second number, effectively dividing the value of the second number by two and four, respectively, to form respective third and fourth numbers. A fourth register receives the numerator of the first number and has at least two stages for representing at least a portion of the value of the numerator in the form of one of two preassigned states which may be assumed by the stages of the fourth register. A coupling means is responsive to the first and second stages of the fourth register and coupled to the second and third registers and a summing means for enabling the summing means for controllably forming an output signal from the values of one of the third, the fourth and the sum of the third and the fourth numbers.
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