COMMON SOURCE LINE CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a common source line control circuit with which the snap back break down of normally-in transistor with the discharge (erasing voltage recovery) of erasing voltage impressed to the bulk of memory cell can be prevented. SOLUTION: A 1st path constituted by serially connecting a normally-on transistor 1 and a normally-off transistor 2 and a 2nd path constituted by serially connecting a normally-on transistor 4, resistor R3 and normally-off transistor 5 are provided parallelly to a common source line CSL. A signal the inverse 56 ERA is turned into Vss by erasure and erasing voltage recovery and turned into Vcc by the others. A signal bar SHOFera is Vss at the time of erasure and transited into Vcc by erasing voltage recovery. It is made into Vcc by the others. Since the 2nd path is first conducted and the erasing voltage is discharged at the time of erasing voltage recovery, the snap back break down of transistor 1 is prevented. Besides, at such a time, the snap back break down of transistor 4 in the 2nd path is surely prevented by the resistor R3 as well.