| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce a read-out error caused by instability of a current to sensitive node of a page buffer. SOLUTION: This memory senses voltage variation of a bit line in accordance with cell data by making a sense currency by a PMOS transistor P1 flow to a per-charged bit line through a separating means N2, and reads out data. As a reading means in which cell data read out by changing theoretically sense nodes BSO0-31 conforming to voltage variation of a bit line is delayed and sensed without performing latch-operation, an inverted is provided. The inverter comprises first conduction type transistors P2-P4 responding to voltage of a sense node and a column address decoding signal and a second conduction type transistor N3. Possibility of latching error data caused by instability of load current of a transistor P1 with wrong timing is prevented, and an error does not occur.</p> |
