| 摘要 |
PROBLEM TO BE SOLVED: To suppress the phase difference between distribution destinations to about a steady phase error and, at the same time, to minimize the size of a memory which absorbs the phase difference. SOLUTION: A master PLL(phase-locked loop) decision circuit 3 controls the switches SW2, SW3, and SW4 of a clock switching control circuit 2 so that the output clock of a clock switching circuit 1 can be introduced to a first PLL 4 having the longest phase following time and the output clock (k) of the PLL 4 can be introduced to a second PLL 5. |
