| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which optimum timing at which a clock signal is inputted to an internal circuit for synchronizing can be set. <P>SOLUTION: A first terminal of a fuse 35 has a first power source potential VSS when it is not cut off, and a second terminal has a second power source potential VDD when it is cut off. A second terminal of a switch 36 has the first power source potential VSS or the second power source potential VDD. An exclusive OR operation circuit 34 outputs exclusive OR A2 with inputted potentials A4, A3 of the first terminal and the second terminal. A switching circuit 33 outputs a second input A0 or exclusive OR A2 as a first output A1 in accordance with a first input TEST3. Finally, a buffer 27 controls a delay time of a clock signal CK0 in accordance with the first output A1. <P>COPYRIGHT: (C)2003,JPO</p> |
