BIT LINE PRECHARGE CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A bit line precharge circuit of a semiconductor memory device is provided to prevent voltage decrease of a precharge voltage generation line while short is generated between a bit line pair and a word line. CONSTITUTION: The first and the second transistors(N50,N51,N52,N53) have a gate connected between the bit line pair and receiving a precharge control signal and transmit a precharge voltage to the bit line pair in response to the above precharge control signal. The third transistor has a gate connected between the bit line pair and receiving the above precharge control signal and makes the level of the bit line pair equal. A channel length of the first and the second NMOS transistors is longer than that of the third transistor, and thus resistance of the first and the second NMOS transistors is higher than that of the third transistor.