发明名称 Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
摘要 The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
申请公布号 US9520362(B2) 申请公布日期 2016.12.13
申请号 US201514706311 申请日期 2015.05.07
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 Lin Chun-Chieh;Su Hung-Wen;Tsai Ming-Hsing;Jang Syun-Ming
分类号 H01L23/528;H01L23/522;H01L29/51;H01L23/532 主分类号 H01L23/528
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A semiconductor device, comprising: a substrate; a first interconnect layer disposed over the substrate; a second interconnect layer disposed over the first interconnect layer, wherein: the second interconnect layer includes a plurality of dielectric segments, a plurality of metal line components interleaving with the dielectric segments, and a plurality of dielectric barrier elements disposed between the dielectric segments and the metal line components; a plurality of vias disposed underneath a first subset of the metal line components; a plurality of dielectric components interleaving with the plurality of vias, wherein the dielectric components are disposed underneath a second subset of the metal line components different from the first subset, and wherein the plurality of vias and the plurality of dielectric components are disposed over the first interconnect layer; and an etch-stop layer disposed above the first interconnect layer but below the plurality of vias and the plurality of dielectric components.
地址 Hsin-Chu TW