Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM

摘要

The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is configured to store the configuration data from the OTP NVM beginning at an address in the RAM corresponding to a read start address to define a timing device configuration in the RAM.

主权项

1. A method for controlling operation of a timing device comprising:
receiving input at the timing device, the input including a start address and an end address; when the input includes a burn address, reading configuration data from a Random Access Memory (RAM) beginning at an address in the RAM corresponding to the burn address and burning the configuration data read from RAM into a one time programmable non volatile memory (OTP NVM) at a location in the OTP NVM corresponding to the start address and the end address; and when the input includes a read start address, reading the configuration data from the OTP NVM beginning at a location in the OTP NVM corresponding to the start address and ending at a location in the OTP NVM corresponding to the end address and storing the configuration data read from the OTP NVM into the RAM beginning at an address in the RAM corresponding to the read start address.