| 摘要 |
A digital receive signal is sampled by an A/D converter, and the position of a point at which the receive signal crosses a reference level is obtained in response to sampling data by an exclusive OR gate. A phase interval between the present sampling point and the point at which the receive signal crosses the reference level is obtained by an arithmetic circuit, and the phase of the present sampling point is obtained in accordance with the position of the crossing point, the phase interval P between the present sampling point and the crossing point obtained by arithmetic circuit, the phase of a preceding sampling point obtained by an I-bit parallel delay circuit, and the phase of a sampling point which is two points preceding to the present sampling point and obtained by an I-bit j-stage parallel delay circuit. A data detection clock signal and digital data are detected in accordance with the computed phase of each sampling point, an MSB of sampling data, and the phase interval between the present sampling point and the point at which the receive signal crosses the reference level.
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