| 发明名称 | Detecting write disturb in multi-port memories | ||
| 摘要 | A circuit includes a memory cell having a first control line and a second control line, the first control line carrying a first control signal, the second control line carrying a second control signal. A first circuit is coupled to the first control line, the second control line, and a node, and a second circuit is coupled to the node and responds to a timing of the first control signal and the second control signal. The first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node, and a logical value of the node signal indicates a write disturb condition of the memory cell. | ||
| 申请公布号 | US9508451(B2) | 申请公布日期 | 2016.11.29 |
| 申请号 | US201514870376 | 申请日期 | 2015.09.30 |
| 申请人 | TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. | 发明人 | Katoch Atul |
| 分类号 | G11C7/00;G11C29/02;G11C7/22;G11C8/16;G11C11/419;G11C29/52 | 主分类号 | G11C7/00 |
| 代理机构 | Hauptman Ham, LLP | 代理人 | Hauptman Ham, LLP |
| 主权项 | 1. A circuit comprising: a memory cell having a first control line and a second control line, the first control line configured to carry a first control signal, the second control line configured to carry a second control signal; a first circuit coupled to the first control line, the second control line, and a node; and a second circuit coupled to the node and configured to respond to a timing of the first control signal and the second control signal, wherein the first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node; anda logical value of the node signal indicates a write disturb condition of the memory cell. | ||
| 地址 | TW | ||