| 摘要 |
PROBLEM TO BE SOLVED: To enable a function determining circuit in an LSI of bonding option to be lessened in current consumption and area occupied by it on a chip. SOLUTION: A DC voltage VREF generated in an LSI and smaller than a power supply voltage VDD but larger than a ground potential is applied to a gate electrode of a PMOS transistor QP1 which forms a function determining circuit. As the gate voltage of the transistor QP1 is set lower than usual, a current flowing through the transistor QP1 is lessened. Therefore, the gate of the transistor QP1 can be lessened in length. When a second PMOS transistor is connected to the transistor QP1 in parallel and made to have a function to feed electrical charge to a node A, the transistor QP1 can be much lessened in area. When a DC voltage such as a reduced voltage generated in an LSI for a certain purpose other than a function determining circuit is used, an area required for providing a dedicated voltage generating circuit is not required, so that the function determining circuit is restrained from increasing in area. |
