| 摘要 |
<p>A digital electronic circuit is operable in an active mode and a low power sleep mode. A power interruption transistor interrupts supply current in the sleep mode. The circuit contains a node that retains a voltage representing stored information in both the active mode and the sleep mode. The stored information indirectly controls control electrodes of a low and high threshold storage transistor. The main current channels of the low threshold storage transistor and the power interruption transistor are coupled in series between the node and the power supply connection. The main current channel of the high threshold storage transistor is connected in parallel with the main current channel of the power interruption transistor, to supply current to the node, if necessary, during the sleep mode. Leakage current is reduced by changing the polarity of the gate source voltage of the power interruption between the active mode and the sleep mode and/or by connecting the main current channel of the high threshold transistor to a further node between the main current channels of the low threshold transistor and the power interruption transistor. In an embodiment, the transistors are part of a slave storage cell in a master slave flip-flop and inverters in the storage cell are kept outside the critical timing paths.</p> |
