发明名称 |
METHOD OF DETECTING FAILURE OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF GENERATING DC TEST PATTERN |
摘要 |
PROBLEM TO BE SOLVED: To solve a problem that a long time is required for test because a conventional test pattern is elongated in order to detect failure of the entire logic circuit, and a problem that a case where the testability does not become 100%, occurs in DC parameter test because an output mode may not be set for a bi-directional pin, and to provide a method of detecting a failure of a semiconductor integrated circuit in which DC parameter test can be carried out efficiently. SOLUTION: The method of detecting failure of a semiconductor integrated circuit is arranged such that a failure is set only for the output pin and the bi-directional pin of the semiconductor integrated circuit and a DC test pattern for detecting that failure is generated. COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2003344512(A) |
申请公布日期 |
2003.12.03 |
申请号 |
JP20020160396 |
申请日期 |
2002.05.31 |
申请人 |
MITSUBISHI ELECTRIC CORP;MITSUBISHI ELECTRIC ENGINEERING CO LTD |
发明人 |
MORITA YASUMASA;TANAKA HIROSHI;KOSAKO YASUSHI |
分类号 |
G01R31/3183;G01R31/28;G01R31/319;G06F17/50;(IPC1-7):G01R31/318 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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