| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To adjust the skews of the clock signals easily to each other by reducing the circuit scale in a semiconductor integrated circuit containing memory cells, such as RAM and the like, and a sequential logic circuit, such as a flip-flop and the like. <P>SOLUTION: The method of designing the layout of a semiconductor integrated circuit comprises a step (a) of inputting a net list indicating the circuit information on the semiconductor integrated circuit into a computer, a step (b) of arranging the circuits contained in the net list, a step (c) of arranging a first clock tree circuit connected to the sequential logic circuit on the basis of a skew adjusting condition of the sequential logic circuit, a step (d) of arranging a second clock tree circuit connected to the memory cell array on the basis of the skew adjusting condition of the memory cell array, and a step (e) of providing interconnecting lines to the circuits contained in the net list and the first and the second clock tree circuit respectively. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
