| 摘要 |
PURPOSE:To perform refresh without decreasing the processing efficiency of a CPU, by performing refresh at the 1st half of one machine cycle and performing access at the latter half. CONSTITUTION:One cycle of the machine cycle is divided into a refresh mode for the prior half and a normal mode for the latter half at refresh and this time of division is controlled with normal/refresh switching signals NOR/REF. When the level of the signals NOR/REF is at L, RAS and CAS signals are risen at the same time, and when the RAS signal drops, a refresh address is given at a switching circuit ADSW as a system address, the row of an RAM only is designated for refresh operation. In the normal mode, a memory control circuit MEM.CONT controls leading and trailing of the RAS signal again. |
