| 摘要 |
<p>A technique for recovering a clock from a digitally encoded communication signal uses a low-Q resonator and limiter for generating a coarse clock signal comprising a series of rectangular pulses at a frequency substantially equal to the clock (though subject to phase jitter), and a filter circuit, such as a phase-locked-loop ('PLL'), preferably employing a Sequential Phase/Frequency Detector to reduce the jitter superimposed on the coarse clock signal, so as to yield a well-behaved clock signal. By using a Sequential Phase/Frequency Detector, acquisition-aid circuitry generally is not required for the PLL.</p> |
