| 摘要 |
A chip verification method, comprising: generation of a verification platform, the verification platform comprising: a modeling layer and an interface layer, the modeling layer comprising a flow model and a register model, and the interface layer comprising a data bus interface agent and a CPU bus interface agent; verification of chips to be tested is carried out by means of the verification platform. The described technical solution resolves the problem of low reusability in verification structures due to the lack of hierarchy in same, thus increasing the reusability of verification structures and enhancing verification efficiency. |
