发明名称 EXPLORADOR DE LINEAS DE ABONADO DE CENTRAL TELEFONICA.
摘要 <p>1363011 Automatic exchange systems INTERNATIONAL STANDARD ELECTRIC CORP 3 Feb 1972 [9 Feb 1971] 5031/72 Heading H4K A subscriber's line scanner is enabled by a control circuit so as to hunt exclusively for calling lines or for parked lines. The latter consist of lines which are receiving busy tone, those which are just released following busy tone and those in a permanent loop condition. The scanner is described in the context of a three stage crossbar network through which a calling and a called line are connected to a local junctor or to incoming/outgoing or special service junctors, the exchange being controlled by a stored programme control which accesses line circuits and junctors via scanners. Line circuit (Fig. 2).-In the free state a subscriber's line L1, L2 is fed by - 48 V and earth via closed contacts A1, A2, whereby points pt1, pt2 and pt3 are respectively at potentials of earth, - 48 V and earth. Consequently capacitor C1 is charged by the potential difference of points pt4, pt5 which are connected by equal high resistances R4, R3 to pt3 and pt1. If the line is now looped, i.e. a calling line, the potentials at pt1, pt2, pt3 are changed to - 16 V, - 32 V, E due to the loop current flow. When the call is placed under a local junctors control via the network connection RC contacts A open and the - 48 V potential via R6 is effective at points pt1 and pt3. However, if the wanted party is busy contacts P1, P2 are closed to inject busy tone from source OCC whereby the potentials at pt1, pt2, pt3 become- 20 V., - 34 V, - 6 V In this situation the line is parked and central control must then decide whether or not it is a faulty line on the basis of how long the busy tone has been supplied, e.g. within a period of 12 minutes not more than four successive scans should result in a parked, looped situation being encountered. When a line releases after receiving busy tone this constitutes a parked, unlooped line so that the relevant potentials are - 6 V, - 48 V and - 6 V On normal release the local junctor apprises central control accordingly so that the A contacts may be closed and the original free state thus obtains once more. Line scanner is effective for supervising 1024 lines whose line circuits EL-or at least those portions thereof referenced st1, st2-are arranged as cross-points in the scanning matrix MC (Fig. 3). The rows of the matrix are arranged in four groups SR0-SR3 each of sixteen wire pairs, e.g. D10.0 to D10.15. The individual pulse generators, i.e. the actual devices D connected to the wire pairs, are addressed by a coincidence of pulses on inlets SR, MS whereby only one row is fully addressed at any one time. The 16 columns of the matrix are connected to read-out DL and logic circuits ER0 which perform an initial processing of the data derived from the line circuits. During any scan-which may be started at any arbitrary line circuit-only half of the sixteen columns are permitted access over leads L0-S7 to a further processing circuit (Fig. 4). Normally the scan runs over only one group 32 of the 64 rows and then stops automatically. It is of course temporarily halted if a line condition change is detected so as to inform central control. Operation.-Central control loads a register R0 (Fig. 4) in the scanner with a 16-bit word consisting of 3 OR bits that specify the type of scan which is to be affected viz. for calling or parked lines; 4 SR bits that specify the group and 4 MS bits that specify the particular row within the group and an SA3 bit which specifies whether it is the first half or the second half of the matrix columns that is to be interrogated. At the same time central control sets bi-stable GO so as to start a local clock HG in the scanner. A decoder D0 decodes the OR bits and produces a calling line scan N or a parked line P instruction for the preliminary and secondary logic circuits ER and REV. Decoders DSR and DMS enable one of the pulse generators D0 in accordance with the SR and MS bits so as to cause +29 V and +18 V pulses to be injected on to row leads St1 and St2 respectively (Fig. 2) of the matrix row associated with the line circuit group under consideration. The capacitors C1, C2 "modify" these pulses in accordance with their state of charge (which itself depends on the looped/ unlooped, free/parked condition of the line to which they are connected). The results of the modification are read-out by read-out circuits DL to produce corresponding 1 or 0 signals. Fig. 6 depicts the value of these signals for the five cases discussed above, viz. free/unlooped; free/looped (i.e. calling); busy on a normal connection; parked/looped (i.e. receiving busy tone or permanent loop); parked/unlooped (i.e. release after busy tone). The logic ER manipulates these signals in different manners in accordance with the calling line N or parked line P scan instructions so as to produce L and S signals therefrom. The results of this manipulation for the chosen half of the 16 line circuits, viz. those marked SA3 or those marked SA3, are then passed over the signal leads L, S and entered in register R1 (Fig. 4). The signals are further processed with the N or P scan instruction by logic REV which produces an output EV if a required condition is encountered (cf. 1 bit in the EV columns in Fig. 6). EV stops the clock and produces a demand to central control which reads out the contents of R0 and R1 so as to identify the lines concerned as well as the condition of these lines thereby to initiate action thereon after consultation with its last loop memory and programme. Thereafter central control restarts the scan. The clock reaches its last stage; enables add-one counter ad31 so that MS and SA3 are each incremented by one whereby another group of 8 line circuits can be interrogated and then resets to zero to permit a new scan to start. When 32 scans have been effected, i.e. all 256 lines in a group taken 8 at a time, the add one circuit stops the clock and the scanner becomes quiescent.</p>
申请公布号 ES399611(A1) 申请公布日期 1975.06.01
申请号 ES19110003996 申请日期 1972.02.09
申请人 STANDARD ELECTRICA, S. A. 发明人
分类号 H04Q3/545;(IPC1-7):04M/ 主分类号 H04Q3/545
代理机构 代理人
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