| 摘要 |
PURPOSE:To increase processing efficiency by changing processing modes according to the uneven distribution of a load. CONSTITUTION:A central processing unit (CPU) 2 consists of the prefetch block 2 (preprocessing block) composed of an instruction prefetch mechanism (IFU) 5, an instruction decoding mechanism (IDU) 6, and an operated data prefetch mechanism (OFU) 7, and the execution block 4 composed of an arithmetic mechanism (EXU) 8, and the IFU5, IDU6, OFU7, and EXU8 perform four-stage pipeline control. In the 1st mode, an instruction succeeding an instruction processed by the EXU8 is processed by the OFU7, and in the 2nd mode, the same instruction is executed by the EXU8 and OFU7 in parallel. |
