发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To prevent fluctuation of a threshold voltage, by converting the upper part of the polycrystalline Si gate electrode of a MOS transistor into an amorphous part, implanting ions for forming P pockets, and preventing penetration of said ions into a gate region. CONSTITUTION:On a P-type Si substrate 21, an element isolating region 22, a gate oxide film layer 23 and a polycrystalline Si gate electrode layer 24 are formed. Therefore, the ions of any of Si, F and O are implanted and an upper part 25 of layer 24 is made amorphous. Then, B-implanted layers 28a and 28b are formed by the implantation of B ions in order to form P-pocket regions 37a and 37b. In order to form N<-> regions 33a and 33b, P-implanted layers 29a and 29b are formed by implanting P ions. Then, by an ordinary method, an oxide film 30 on the side wall of the gate, N<+> regions 34a and 34b, a protecting film 32, electrodes 39 and the like are formed. When B ions are implanted for forming the P-pocket regions, the B ions are not penetrated to the gate region owing to the presence of the amorphous layer 25. Therefore, a channeling phenomenon is not yielded, and fluctuation of a threshold voltage can be prevented.
申请公布号 JPS61191070(A) 申请公布日期 1986.08.25
申请号 JP19850030508 申请日期 1985.02.20
申请人 TOSHIBA CORP 发明人 NAKAHARA MORIYA
分类号 H01L21/033;H01L21/265;H01L21/3215;H01L21/336;H01L29/10;H01L29/78 主分类号 H01L21/033
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