发明名称 SEMICONDUCTOR MEMORY
摘要 PURPOSE:To reduce a noise level generated in a power source voltage wirings or a ground wire of a circuit by dividing two memory mats at right and left sides of an X-address decoder, and symmetrically assigning addresses to the divided memory. CONSTITUTION:Two memory mats M-ARYR, M-ARYL are disposed at right and left sides on X-address decoder XDCR as a center. The mats are divided in data line direction to form a plurality of memory arrays M0-M7. Addresses are assigned symmetrically to the memory arrays at the decoder XDCR as a center. Thus, the wiring length for connecting between the memory arrays of pairs become different according to word line length at the decoder as a center in the two mats. As a result, since a current flowed to the power source voltage line of an integrated circuit or the ground line of a circuit is averaged, a noise level can be reduced.
申请公布号 JPS61218166(A) 申请公布日期 1986.09.27
申请号 JP19850058406 申请日期 1985.03.25
申请人 HITACHI CHIYOU LSI ENG KK;HITACHI LTD 发明人 KUNITO SOUICHI;NAKAMURA HIDEAKI;KUBODERA MASAAKI;KONDO NAOHITO;NOSAKA TOSHIO
分类号 H01L21/822;G11C11/34;G11C11/401;G11C11/407;G11C11/409;G11C11/41;G11C11/417;H01L27/04;H01L27/10 主分类号 H01L21/822
代理机构 代理人
主权项
地址