发明名称 FORMING METHOD FOR WIRING PATTERN OF GATE ARRAY LSI
摘要 PURPOSE:To prevent a local power source potential variation position or an abnormal power source current density rising position from occurring by forming and inserting a reinforcing power source wiring pattern in response to a logic configuration, a logic block disposition. CONSTITUTION:A reinforcing power source pattern 51 is formed in response to the temporary disposition of a logic block 41 to be disposed on a basic cell row 31. Then, items of judging the necessity of the reinforcing power source and forming the reinforcing power source pattern are provided. Since allowable number or more of power gates are arranged on the row 31, a basic cell row in which a power source potential varies or a power source current density becomes allowable limit or more is employed as a vacant logic block 71, and the disposition of the logic block is corrected. Then, the pattern 51 which is passed and wired to the block 71 is formed.
申请公布号 JPH01128542(A) 申请公布日期 1989.05.22
申请号 JP19870285362 申请日期 1987.11.13
申请人 HITACHI LTD;HITACHI MICRO COMPUT ENG LTD 发明人 HASHIDA MITSUYOSHI;KAJIKAWA TAKANOBU
分类号 H01L21/3205;H01L21/82;H01L23/52;H01L27/118 主分类号 H01L21/3205
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