METHOD AND APPARATUS FOR EFFICIENT STORE/RESTORE OF STATE INFORMATION DURING A POWER STATE TRANSITION

摘要

A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for internal state information of a power domain; ii) respective addresses of a memory where the internal state information is stored when the power domain is powered down; and, iii) meta data for transferring the state information between the power domain and where the internal state information is stored when the power domain is powered down.

主权项

1. A processor comprising:
a plurality of power domains including a first power domain for a first processor component and a second power domain for a second processor component; and streamlining circuitry to:
obtain from a memory, for a power state transition from a first power state to a second power state, respective addresses for:
internal state information of each power domain that is enabled in the first power state, andinternal state information of each power domain that is to be enabled in the second power state, andcompare the respective addresses for overlap to determine which of the plurality of power domains are to have their internal state information stored.