发明名称 WIRING BOARD AND ITS MANUFACTURING METHOD, AND ELECTRIC DEVICE
摘要 PROBLEM TO BE SOLVED: To solve the problem that, when an evaporation metal layer is used instead of a conventional electroless plating layer in order to form a microfabricated interconnection of 15μm or less in a semi-additive method, the evaporation metal layer is insufficiently formed on the wall surface of a through-hole and thereby an electrolytic plating layer to be formed continuously on the top face of the through-hole is insufficiently formed, resulting in a decline in conduction reliability. SOLUTION: A wiring board comprises insulation layers 9 which at least contain resin, interconnection conductor layers 15 each of which is formed on the surface of each insulation layer 9, and via conductor layers 13 each of which is extended through each insulation layer 9 to connect the interconnection conductor layers 15 separated by each insulation layer 9. Each of the interconnection conductor layers 15 is constructed by forming an evaporation metal layer 15a and an electrolytic plating layer 15b in order on a principal plane of each insulation layer 9. Each of the via conductor layers 13 is constructed by forming an electroless copper plating layer 13a, an evaporation metal layer 13b, and an electrolytic plating layer 13c in order in a through-hole 11 formed in each insulation layer 9. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005191112(A) 申请公布日期 2005.07.14
申请号 JP20030428073 申请日期 2003.12.24
申请人 KYOCERA CORP 发明人 OTA KENICHI;MIYATANI ISAO
分类号 H05K1/11;H05K3/40;H05K3/46;(IPC1-7):H05K1/11 主分类号 H05K1/11
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