SHIFT REGISTER UNIT, GATE DRIVER CIRCUIT AND DISPLAY PANEL

摘要

The present disclosure relates to a shift register, a gate driver circuit and a display panel. The shift register includes first to eighth transistors and first and second capacitors. In the exemplary embodiments of the present disclosure, a shift register unit is composed of a relatively small number of transistors and capacitors, and thus the wiring areas occupied by the shift register unit and the gate driver circuit composed of a plurality of the shift register units can be reduced, thereby providing technical support for designing display panels with higher resolution and narrower bezel. Meanwhile, because the shift register unit and the gate driver circuit have a relatively simple structure, the manufacturing processes can be simplified and thereby costs can be reduced.

主权项

1. A shift register unit, comprising:
a first switching element that is switched on in response to an input signal so as to provide the input signal to a first node; a second switching element that is switched on in response to a first clock signal so as to provide a first voltage to the first node; a third switching element that is switched on in response to the first clock signal so as to provide the first voltage to a second node; a fourth switching element that is switched on in response to a third clock signal so as to provide the input signal to the second node; a fifth switching element that is switched on in response to a signal at the second node so as to input the first voltage to a third node; a sixth switching element that is switched on in response to the first clock signal so as to provide a second voltage to the third node; a seventh switching element that is switched on in response to a signal at the third node so as to provide the first voltage to an output signal terminal; an eighth switching element that is switched on in response to a signal at the first node so as to provide a second clock signal to the output signal terminal; a first capacitor coupled between the first voltage and the second node; and a second capacitor coupled between the first node and the output signal terminal.