Multilevel memory stack structure employing support pillar structures

摘要

A first stack of alternating layers including first electrically insulating layers and first sacrificial material layers is formed with first stepped surfaces. First memory openings can be formed in a device region outside of the first stepped surfaces, and first support openings can be formed through the first stepped surfaces. The first memory openings and the first support openings can be filled with a sacrificial fill material. A second stack of alternating layers including second electrically insulating layers and second sacrificial material layers can be formed over the first stack. Inter-stack memory openings including the first memory openings can be formed in the device region, and inter-stack support openings including the first support openings can be formed in a steppes surface region. Memory stack structures and support pillar structure are simultaneously formed in the inter-stack memory openings and the inter-stack support openings, respectively.

主权项

1. A monolithic three-dimensional memory device comprising:
a lower stack structure comprising a first stack of alternating layers including first electrically insulating layers and first electrically conductive layers and located over a substrate; an upper stack structure comprising a second stack of alternating layers including second electrically insulating layers and second electrically conductive layers and located over the lower stack structure; an etch stop dielectric layer located within the lower stack structure and overlying the first stack of alternating layers and contacting a bottom surface of the upper stack structure and comprising a dielectric material having a different composition than the first electrically insulating layers; a plurality of memory stack structures including respective vertical semiconductor channels, wherein a bottommost portion of each vertical semiconductor channel is electrically shorted to a source region located below the lower stack, and an upper portion of each vertical semiconductor channel is electrically shorted to a drain contact via structure overlying the vertical semiconductor channel; and at least one support pillar structure located within a stepped surface region of the lower and upper stack structures, comprising a same set of materials as the plurality of memory stack structures.