LOW COST, FLEXIBLE SPACE GPS RECEIVER TECHNOLOGY DEVELOPMENT PLATFORM

摘要

A Field Programmable Gate Array (FPGA) evaluation board may include a firmware/software architecture that facilitates easier prototyping of new GPS receiver designs. A single reprogrammable FPGA with an integrated soft processor and spare logic resources may be targeted to expand the GPS receiver design. The system may operate on an FPGA evaluation board with the ability to integrate easily with various types of analog/radio frequency (RF) hardware. A hardware platform with a variety of connections to a computer may be utilized to be able to read telemetry from the receiver and analyze the performance.

主权项

1. A Field Programmable Gate Array (FPGA) evaluation board, comprising:
an FPGA running Global Positioning System (GPS) firmware flight code, wherein the FPGA comprises:
an integrated soft processor running GPS receiver flight software, the GPS receiver flight software configured to operate a navigation system on a space vehicle, andspare logic resources to expand a GPS receiver flight design, and the FPGA integrates with a plurality of different types of analog/radio frequency (RF) hardware and tests functionality of the plurality of different types of analog/RF hardware via the GPS receiver firmware and software.