EFFICIENT HARDWARE INSTRUCTIONS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSORS: FAST FIXED-LENGTH VALUE COMPRESSION

摘要

Methods and apparatuses for determining set-membership using Single Instruction Multiple Data (“SIMD”) architecture are presented herein. Specifically, methods and apparatuses are discussed for compressing or packing, in parallel, multiple fixed-length values into a stream of multiple variable-length values using SIMD architecture.

主权项

1. A processor configured to compress, within the processor, a vector of fixed-length values to produce a vector of variable-length values;
wherein each fixed-length value in the vector of fixed-length values is a variable-length value that has been padded, as needed, to achieve a particular fixed length; wherein each fixed-length value in the vector of fixed-length values corresponds to a length value in a vector of lengths; wherein each length value in the vector of lengths indicates an unpadded length of the fixed-length value, which corresponds to the length value, in the vector of fixed values; wherein the processor is configured to:
store fixed-length values from the vector of fixed-length values in a series of subregisters in a SIMD register; andrespond to one or more instructions by:
storing each value, in the series of subregisters, into the vector of variable-length values based on the vector of lengths;wherein each variable-length value in the vector of variable-length values is unpadded.