Clock generation for timing communications with ranks of memory devices

摘要

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

主权项

1. A memory system, comprising:
a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank; and a memory controller comprising:
a clock generator to generate a first signal; anda timing circuit to generate a second signal from the first signal to time data transfer communications with the first and second memory devices, the timing circuit to adjust a phase of the first signal to generate the second signal when the memory controller transitions from a data transfer communication with the first memory device to a data transfer communication with the second memory device, the second signal having a phase that is based on calibration data associated with the second memory device, wherein the calibration data is to be established based on a strobe signal received from the second memory device.