Level shift driver circuit capable of reducing gate-induced drain leakage current

摘要

A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

主权项

1. A level shift driver circuit, comprising:
a level shift circuit comprising:
a first system voltage terminal (VPP) for receiving a driving voltage;a second system voltage terminal (VSS) for receiving a system base voltage;a first input terminal for receiving a first input signal (IN);a second input terminal for receiving a second input signal (ZIN), wherein the second input signal is an inverse signal of the first input signal; anda first output terminal; and a first driver circuit comprising:
a first P-type transistor having a first terminal coupled to the first system voltage terminal, a second terminal, and a control terminal coupled to the first output terminal;a second P-type transistor having a first terminal coupled to the second terminal of the first P-type transistor, a second terminal, and a control terminal;a first N-type transistor having a first terminal coupled to the second terminal of the second P-type transistor, a second terminal, and a control terminal for receiving an operative voltage;a second N-type transistor having a first terminal coupled to the second terminal of the first N-type transistor, a second terminal coupled to the second system voltage terminal, and a control terminal coupled to the first output terminal; andat least one seventh P-type transistor coupled in series between the first P-type transistor and the second P-type transistor; wherein: when the first input signal is at the operative voltage, a voltage level of the first output terminal is at the system base voltage; and when the first input signal is at the system base voltage, the voltage level of the first output terminal is at the driving voltage.