CURRENT-MODE CLOCK DISTRIBUTION

摘要

Current-mode signaling for a one-to-many clock signal distribution providing significantly less dynamic power use and improved noise immunity compared to traditional VM signaling schemes.

主权项

1. A current mode flip-flop, comprising:
a first current mirror for receiving a voltage reference and for producing a first reference current in response to said voltage reference; a second current mirror for producing a second reference current; a current input for modifying said second reference current; a current comparator for producing a difference current between said first reference current and said modified second reference current; an inverting amplifier for converting said difference current into a logic level voltage; a pulse shaper receiving said logic level voltage and for applying a delayed version to said current comparator to thereby form a clock signal having a pulse duration; a register stage for receiving a data signal and said clock signal; and a storage cell for storing data when said clock signal occurs.