Memory controller, computing device with a memory controller, and method for calibrating data transfer of a memory system

摘要

A memory controller comprises a connection interface connected or connectable to a memory. The memory controller is arranged to read data from the memory via the connection interface. The memory controller further comprises a clock unit arranged to provide a data transfer clock signal having a first frequency. The data transfer clock signal may be provided to the memory via the connection interface. The data transfer clock signal is arranged for clocking a data transfer from the memory to the memory controller via the connection interface as well as an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an over-sampled calibration data pattern. The second frequency is larger than the first frequency. The memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.

主权项

1. A memory controller, comprising:
a connection interface connected or connectable to a memory, the memory controller being arranged to read data from the memory via the connection interface; a clock unit arranged to provide a data transfer clock signal having a first frequency, wherein the data transfer clock signal is provided to the memory via the connection interface, the data transfer clock signal being arranged for clocking a data transfer from the memory to the memory controller via the connection interface; an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface at a second frequency to provide an oversampled calibration data pattern, the second frequency being larger than the first frequency, and wherein the calibration data pattern includes a predetermined sequence of bits; wherein the memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller based on the oversampled calibration data pattern.