PROCESSOR APPARATUS WITH PROGRAMMABLE MULTI PORT SERIAL COMMUNICATION INTERCONNECTIONS

摘要

A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through a gigabit Ethernet interface provided by protocol processor integrated as part of the chip. The protocol processor encapsulates the memory address and control information like Read, Write, number of successive bytes etc, as an Ethernet packet for communication among the processor and memory chips that are located on the same motherboard, or even on different circuit cards. In one embodiment, the communication over head of the Ethernet protocol is further reduced by using an enhanced Ethernet protocol with shortened data frames within a constrained neighborhood, and/or by utilizing a bit stream switch where direct connection paths can be established between elements that comprise the computing or communication architecture.

主权项

1. An apparatus implementing a computing and communication chip architecture for integrated circuitry, comprising:
at least processor cores; and, at least a pair of external ports; and at least one switch operably connected to the said processor core and the said pair of external ports; and, the said processor core and the said pair of external ports and the said switch are collocated on the semiconductor die package; wherein, the said processor core is adopted to send and receive serial communication protocol data packets using a parallel bus to programmable serial interface converter; and, the said processor core is adopted to communicate with external devices using packetized serial communication; and, the said switch is adopted for packetized serial communication among the said processor cores and the said pair of external ports; and, the said switch is adopted to provide translation between multiple serialized protocols; and, each of the said pair of external ports is adopted to provide a predefined serial communications interface.