发明名称 PIXEL SELECTION CONTROL METHOD, DRIVING CIRCUIT, DISPLAY APPARATUS AND ELECTRONIC INSTRUMENT
摘要 A pixel selection control method, driving circuit, display apparatus and electronic instrument are disclosed. A driving circuit includes a logic circuit configured to receive a reference signal associated with a line of pixels. The reference signal has a first logic level or a second logic level. The driving circuit also includes a switch circuit configured to receive the reference signal and an enable signal, and to provide the enable signal to the logic circuit when the reference signal is at the first logic level. A display apparatus may be provided that includes the driving circuit.
申请公布号 US2016148567(A1) 申请公布日期 2016.05.26
申请号 US201615009879 申请日期 2016.01.29
申请人 Sony Corporation 发明人 Tomida Masatsugu;Omoto Keisuke
分类号 G09G3/32 主分类号 G09G3/32
代理机构 代理人
主权项 1. A display apparatus, comprising: a plurality of pixels including a first pixel and a second pixel, each of the first pixel and the second pixel having a light emitting element, a pixel capacitor, a driving transistor, and a sampling transistor; and a driving circuit configured to control the plurality of pixels, the driving circuit comprising: a first logic circuit configured to output a first control signal to the first pixel;a second logic circuit configured to output a second control signal to the second pixel;a first switching transistor configured to supply a part of an enable signal to an input terminal of the first logic circuit according to a first reference signal; anda second switching transistor configured to supply another part of the enable signal to an input terminal of the second logic circuit according to a second reference signal, wherein the first switching transistor has a gate terminal configured to receive the first reference signal, a second terminal configured to receive the enable signal, and a third terminal coupled to a first capacitor and the input terminal of the first logic circuit, and wherein the second switching transistor has a gate terminal configured to receive the second reference signal, a second terminal configured to receive the enable signal, and a third terminal coupled to a second capacitor and the input terminal of the second logic circuit.
地址 Tokyo JP
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