发明名称 DISPLAY PANEL, GATE DRIVER AND CONTROL METHOD
摘要 A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.
申请公布号 US2016118009(A1) 申请公布日期 2016.04.28
申请号 US201514644692 申请日期 2015.03.11
申请人 AU Optronics Corporation 发明人 LIN Chih-Lung;DU Yuan-Wei;CHEN Fu-Hsing;TU Chun-Da
分类号 G09G3/36;H03K19/0185 主分类号 G09G3/36
代理机构 代理人
主权项 1. A display panel, comprising: a plurality of gate lines; and a gate driver comprising a plurality of series-coupled driving stages, wherein each of the series-coupled driving stages is electrically coupled to a corresponding gate line of the gate lines, and an N-th stage of the series-coupled driving stages comprises: a driving unit configured to selectively transmit a first clock signal according to a control voltage level of a control node to output a first gate-driving signal; andan input control unit configured to selectively transmit a second gate-driving signal outputted from an (N−1)-th stage of the series-coupled driving stages to the control node according to a second clock signal, so as to adjust the control voltage level to one of a first voltage level and a second voltage level, wherein N is a positive integer, and the first voltage level is lower than the second voltage level, wherein a predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal, and the input control unit pulls the control voltage level to the first voltage level during the predetermined time interval.
地址 HSIN-CHU TW