发明名称 半導体メモリ回路用の磁気トンネル接合要素を含む調整可能基準回路
摘要 A circuit includes a first reference pair that includes a first path and a second path. The first path includes a first magnetic tunnel junction (MTJ) element, and the second path includes a second MTJ element. The circuit further includes a second reference pair that includes a third path and a fourth path. The third path includes a third MTJ element, and the fourth path includes a fourth MTJ element. The first reference pair and the second reference pair are tied together in parallel. A reference resistance of the circuit is based on a resistance of each of the first, second, third, and fourth MTJ elements. The reference resistance of the circuit is adjustable by adjusting a resistance of one of the MTJ elements.
申请公布号 JP5908165(B2) 申请公布日期 2016.04.26
申请号 JP20150510502 申请日期 2013.05.06
申请人 クアルコム,インコーポレイテッド 发明人 シャ・リ;ジュン・ピル・キム;テヒュン・キム
分类号 G11C11/15 主分类号 G11C11/15
代理机构 代理人
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