| 摘要 |
This application disclosed a low voltage threshold integrated circuit including a substrate, one or more Schottky barrier diodes (SBDs) formed on the substrate, and two or more complementary transistors formed on the substrate. At least one of the SBDs is integrated within a substantially shallow diffusion bed associated with a drain of at least one of the complementary transistors, and shares a common terminal with the at least one of the complementary transistors. In some implementations, the integrated circuit includes a static random access memory (SRAM) array further including a plurality of bit cells. At least one of the bit cells includes two SBDs, and a latch formed from two cross-coupled inverters each including two CMOS transistors. One of the two SBDs is integrated in a substantially shallow diffusion bed associated with a drain of one of the CMOS transistors of the cross-coupled inverters. |
