| 发明名称 | Power gated and voltage biased memory circuit for reducing power | ||
| 摘要 | A circuit system includes: a plurality of memory blocks; a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks; a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; and a control circuit configured to control the power supply circuit and the plurality of first power supply switches, wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether the first power supply switches are in a supplying state or a blocking state. | ||
| 申请公布号 | US9310878(B2) | 申请公布日期 | 2016.04.12 |
| 申请号 | US201313939344 | 申请日期 | 2013.07.11 |
| 申请人 | FUJITSU LIMITED | 发明人 | Watanabe Yasuhiro;Kawakami Kentaro |
| 分类号 | G06F1/32 | 主分类号 | G06F1/32 |
| 代理机构 | Staas & Halsey LLP | 代理人 | Staas & Halsey LLP |
| 主权项 | 1. A circuit system comprising: a plurality of memory blocks; a power supply circuit configured to supply operating power and substrate power to the plurality of memory blocks; a plurality of first power supply switches configured to control whether or not the operating power is supplied from the power supply circuit to the plurality of memory blocks; and a control circuit configured to control the power supply circuit and the plurality of first power supply switches, wherein the control circuit changes a voltage of the operating power to be supplied by the power supply circuit and a voltage of the substrate power to be supplied by the power supply circuit, based on a state of whether each of the plurality of first power supply switches is in a supplying state or a blocking state. | ||
| 地址 | Kawasaki JP | ||