Reconfigurable load-reduced memory buffer

摘要

A memory module can include a data buffer having a data bus interface and a dynamic random access memory (DRAM) coupled to the data buffer. The memory module may also include a switch connected in parallel with the data buffer, wherein the switch can selectively bypass the data buffer. In one example, the memory module also includes a registered buffer having an address bus interface, where the switch may selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.

主权项

1. A memory module comprising:
a data buffer having a data bus interface; a dynamic random access memory coupled to the data buffer; a switch connected in parallel with the data buffer, the switch to selectively bypass the data buffer when the data buffer is powered down and the memory module is being addressed; and a registered buffer having an address bus interface, wherein the switch is to selectively bypass the data buffer based on a program signal obtained from an address bus via the address bus interface.