发明名称 |
Method for manufacturing CMOS device with high-k dielectric layers and high-k cap layers formed in different steps |
摘要 |
A method for manufacturing a semiconductor device may include the following steps: preparing a substrate having a PMOS region and an NMOS; forming a first gate trench on the PMOS region; forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench on the NMOS region; forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer that are positioned on a side of the first gate trench; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer that are positioned on a side of the second gate trench. |
申请公布号 |
US9299619(B2) |
申请公布日期 |
2016.03.29 |
申请号 |
US201414559553 |
申请日期 |
2014.12.03 |
申请人 |
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION |
发明人 |
Zhao Jie |
分类号 |
H01L21/8238;H01L21/311;H01L29/66;H01L29/51 |
主分类号 |
H01L21/8238 |
代理机构 |
Innovation Counsel LLP |
代理人 |
Innovation Counsel LLP |
主权项 |
1. A method for manufacturing a semiconductor device, the method comprising:
preparing a semiconductor substrate that includes a PMOS region for forming a PMOS structure and includes an NMOS region for forming an NMOS structure; forming an interlayer dielectric layer on the semiconductor substrate; forming a first gate trench in the interlayer dielectric layer and on the PMOS region; sequentially forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first gate trench; forming a second gate trench in the interlayer dielectric layer and on the NMOS region; sequentially forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second gate trench; removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer, wherein the portion of the first high-k dielectric layer and the portion of the first high-k cap layer are positioned inside the first gate trench and overlap a side of the first gate trench, and wherein the side of the first gate trench is not parallel to the top surface of the semiconductor substrate; and removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer, wherein the portion of the second high-k dielectric layer and the portion of the second high-k cap layer are positioned inside the second gate trench and overlap a side of the second gate trench, and wherein the side of the second gate trench is not parallel to the to surface of the semiconductor substrate. |
地址 |
CN |