主权项 |
1. A system for statistical static timing analysis (SSTA) of a digital electronic design, the computer program product comprising:
one or more computer processors, one or more computer-readable storage media, and program instructions stored on the one or more computer-readable storage media for execution by at least one of the one or more computer processors, the program instructions comprising: program instruction to propagate, using a computer, a signal label from a signal source to a cycle time dependent timing test, the signal label comprising at least one of:
a signal source identifier, anda signal path cycle adjust information; program instructions to identify, at each input of the cycle time dependent timing test, which timing values of the signal label are needed to compute a downstream cycle time independent timing test; program instruction to propagate back from the cycle time dependent timing test to the signal source a flag indicating the identified timing values of the signal label needed to compute the downstream cycle time independent timing test; and program instruction to compute timing data only for the identified values of the signal label which are needed to compute the downstream cycle time independent timing test. |