Non-Volatile Memory with Multi-Word Line Select for Defect Detection Operations

摘要

A stress mode for use in testing non-volatile memory arrays for a number of types of defects is described. More specifically, a multi-word line select option for a given block can be used for a group of selected word lines to be set to the a programming or other high voltage, while the unselected word lines of the block are set to a pass voltage to minimize electric field differences in order to avoid disturb. For example, a group of selected word lines could number 4, 8 or 16. The multi-word line option can be applied to one block per plane, so that if there are two memory planes, for example, two such blocks can be selected simultaneously for the multi-word line option for those blocks.

主权项

1. A non-volatile memory circuit, comprising:
an array of non-volatile memory cells formed according to a NAND architecture as a plurality of blocks, each block formed of a plurality of NAND strings having multiple memory cells connected in series and connected along word lines; bias circuitry providing bias voltage levels for use in the operation of the array; and decoding circuitry whereby the bias circuit is connectable to the array to selectively apply the bias voltage levels thereto, wherein during a programming operation the decoding circuitry applies a programming voltage to a selected word line of a selected block while applying a pass voltage to non-selected word lines of the selected block, the programming voltage being higher that the pass voltage, and wherein during a stress operation the decoding circuitry applies a stress voltage concurrently to a first plurality of selected word lines of a selected block while applying the pass voltage to one or more non-selected word lines of the selected block, the stress voltage being higher than the pass voltage, and where the first plurality of selected word lines are a set of adjacent word lines.