DATA PROCESSING APPARATUS AND METHOD OF PROCESSING DATA

摘要

A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.

主权项

1. A data processing apparatus, comprising:
an inputting portion configured to receive a serial data formed of a sequence of serial data blocks of N bits (N is a natural number greater than 2) and including a clock bit; a first retrieving portion configured to retrieve and obtain a data of K bits (K is a natural number greater than N, K>N) from each of the serial data blocks as a first retrieved data; a second retrieving portion configured to retrieve and obtain a data of L bits (L is a difference between N and K, L=K−N) from each of the serial data blocks as a second retrieved data; a clock determining portion configured to determine whether the clock bit is included in one of the first retrieved data and the second retrieved data; a first serial parallel converting portion configured to perform parallel conversion to one of the first retrieved data and the second retrieved data that includes the clock bit according to a determination result of the clock determining portion so that the first serial parallel converting portion obtains a first parallel data; a second serial parallel converting portion configured to perform parallel conversion to the other one of the first retrieved data and the second retrieved data that does not include the clock bit according to the determination result of the clock determining portion so that the second serial parallel converting portion obtains a second parallel data; and a combining portion configured to combine the first parallel data and the second parallel data to output a parallel data of N bits.