Techniques and configurations to reduce transistor gate short defects

摘要

Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

主权项

1. An apparatus, comprising:
a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material; a gate plug disposed between a first portion of a first individual line of the individual lines and a second portion of the first individual line to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device; a contact electrode material disposed between the first individual line and a second individual line of the individual lines, wherein at least a portion of the contact electrode material is in direct contact with the gate plug; and a contact plug disposed between the first individual line and the second individual line to isolate source or drain contacts of the first transistor device from source or drain contacts of the second transistor device, wherein the contact plug comprises a first electrically insulative material and the gate plug comprises a second electrically insulative material that has a different chemical composition than the first electrically insulative material.